A Representative Framework for Implementing Quantum Finite Automata on Real Devices

TL;DR

This paper develops a practical framework for implementing quantum finite automata algorithms on real gate-based quantum devices, optimizing for gate count and circuit depth based on hardware constraints.

Contribution

It introduces a compilation and optimization framework that reduces CNOT gates and circuit depth for quantum automata algorithms on existing quantum hardware.

Findings

Reduced CNOT gate count through compilation techniques

Optimized algorithms for specific hardware topologies

Demonstrated feasibility on real quantum devices

Abstract

We present a framework for the implementation of quantum finite automata algorithms designed for the language $ MOD_p = \{ a^{i\cdot p } \mid i \geq 0 \}$ on gate-based quantum computers. First, we compile the known theoretical results from the literature to reduce the number of CNOT gates. Second, we demonstrate techniques for modifying the algorithms based on the basis gates of available quantum hardware in order to reduce circuit depth. Lastly, we explore how the number of CNOT gates may be reduced further if the topology of the qubits is known.