CircuitVAE: Efficient and Scalable Latent Circuit Optimization

TL;DR

CircuitVAE introduces a scalable, sample-efficient search algorithm that embeds digital circuit design in a continuous space, enabling the creation of larger, faster, and more efficient circuits than existing methods.

Contribution

The paper presents CircuitVAE, a novel gradient-based optimization approach for digital circuit design that outperforms traditional algorithms and commercial tools in efficiency and scalability.

Findings

Successfully designed large binary adders with fewer samples.

Outperformed reinforcement learning and genetic algorithms in circuit size and speed.

Achieved state-of-the-art adder designs in real-world chip testing.

Abstract

Automatically designing fast and space-efficient digital circuits is challenging because circuits are discrete, must exactly implement the desired logic, and are costly to simulate. We address these challenges with CircuitVAE, a search algorithm that embeds computation graphs in a continuous space and optimizes a learned surrogate of physical simulation by gradient descent. By carefully controlling overfitting of the simulation surrogate and ensuring diverse exploration, our algorithm is highly sample-efficient, yet gracefully scales to large problem instances and high sample budgets. We test CircuitVAE by designing binary adders across a large range of sizes, IO timing constraints, and sample budgets. Our method excels at designing large circuits, where other algorithms struggle: compared to reinforcement learning and genetic algorithms, CircuitVAE typically finds 64-bit adders which are smaller and faster using less than half the sample budget. We also find CircuitVAE can design state-of-the-art adders in a real-world chip, demonstrating that our method can outperform commercial tools in a realistic setting.