Python-based DSL for generating Verilog model of Synchronous Digital Circuits

TL;DR

This paper introduces a Python-based DSL that enables users to model synchronous digital circuits with high-level constructs, automatically generating synthesizable Verilog suitable for FPGA and ASIC development.

Contribution

The paper presents a novel Python-based DSL for modeling digital circuits with explicit cycle boundaries, producing synthesizable Verilog, and demonstrates its application in various complex domains.

Findings

Successfully generated Verilog from high-level Python models

Applied DSL to cryptography, vision, and signal processing examples

Framework supports integration with existing RTL and hardware flows

Abstract

We have designed a Python-based Domain Specific Language (DSL) for modeling synchronous digital circuits. In this DSL, hardware is modeled as a collection of transactions -- running in series, parallel, and loops. When the model is executed by a Python interpreter, synthesizable and behavioural Verilog is generated as output, which can be integrated with other RTL designs or directly used for FPGA and ASIC flows. In this paper, we describe - 1) the language (DSL), which allows users to express computation in series/parallel/loop constructs, with explicit cycle boundaries, 2) the internals of a simple Python implementation to produce synthesizable Verilog, and 3) several design examples and case studies for applications in post-quantum cryptography, stereo-vision, digital signal processing and optimization techniques. In the end, we list ideas to extend this framework.