Real-time Digital RF Emulation -- II: A Near Memory Custom Accelerator

TL;DR

This paper presents a near memory hardware accelerator for real-time RF system emulation, utilizing ASIC and FPGA implementations to achieve high bandwidth, low latency, and extensive emulation range.

Contribution

It introduces a novel direct path computational model and demonstrates its effectiveness through ASIC and FPGA prototypes for real-time RF emulation.

Findings

ASIC prototype achieves 518 MHz per channel bandwidth.

ASIC system supports 9.5 km emulation range with 0.24 μs latency.

FPGA implementation supports up to 27.3 km range at 215 MHz bandwidth.

Abstract

A near memory hardware accelerator, based on a novel direct path computational model, for real-time emulation of radio frequency systems is demonstrated. Our evaluation of hardware performance uses both application-specific integrated circuits (ASIC) and field programmable gate arrays (FPGA) methodologies: 1). The ASIC testchip implementation, using TSMC 28nm CMOS, leverages distributed autonomous control to extract concurrency in compute as well as low latency. It achieves a $518$ MHz per channel bandwidth in a prototype $4$-node system. The maximum emulation range supported in this paradigm is $9.5$ km with $0.24$ $\mu$s of per-sample emulation latency. 2). The FPGA-based implementation, evaluated on a Xilinx ZCU104 board, demonstrates a $9$-node test case (two Transmitters, one Receiver, and $6$ passive reflectors) with an emulation range of $1.13$ km to $27.3$ km at $215$ MHz bandwidth.