FPGA-based Distributed Union-Find Decoder for Surface Codes

TL;DR

This paper presents a scalable FPGA-based distributed Union-Find decoder for surface codes that significantly accelerates quantum error correction, achieving sublinear decoding times with increasing code distance.

Contribution

It introduces a novel distributed UF decoder architecture called Helios, enabling faster decoding with FPGA implementation and demonstrating scalability up to d=51.

Findings

Decoding time decreases as code distance increases.

Achieved sub-12 ns decoding for d=21 on FPGA.

Scalable decoding up to d=51 with 544 ns latency.

Abstract

A fault-tolerant quantum computer must decode and correct errors faster than they appear to prevent exponential slowdown due to error correction. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than $O(d^3)$. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to $d$, given $O(d^3)$ parallel computing resources. The decoding time per measurement round decreases as $d$ increases, the first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using a Xilinx VCU129 FPGA, we successfully implement $d$ up to 21 with an average decoding time of 11.5 ns per measurement round under 0.1\% phenomenological noise, and 23.7 ns for $d=17$ under equivalent circuit-level noise. This performance is significantly faster than any existing decoder implementation. Furthermore, we show that Helios can optimize for resource efficiency by decoding $d=51$ on a Xilinx VCU129 FPGA with an average latency of 544ns per measurement round.