Continuous-Time Digital Twin with Analogue Memristive Neural Ordinary Differential Equation Solver

TL;DR

This paper introduces a memristive neural ODE solver for digital twins that captures continuous dynamics, significantly improves speed and energy efficiency, and is validated on memristor and Lorenz96 models.

Contribution

It presents a novel analogue memristor-based neural ODE approach for digital twins, overcoming the von Neumann bottleneck and enabling scalable, energy-efficient continuous-time modeling.

Findings

Achieves 4.2-fold speedup and 41.4-fold energy reduction on memristor twin

Demonstrates 12.6-fold speedup and 189.7-fold energy efficiency on Lorenz96 dynamics

Maintains acceptable error margins while significantly improving performance

Abstract

Digital twins, the cornerstone of Industry 4.0, replicate real-world entities through computer models, revolutionising fields such as manufacturing management and industrial automation. Recent advances in machine learning provide data-driven methods for developing digital twins using discrete-time data and finite-depth models on digital computers. However, this approach fails to capture the underlying continuous dynamics and struggles with modelling complex system behaviour. Additionally, the architecture of digital computers, with separate storage and processing units, necessitates frequent data transfers and Analogue-Digital (A/D) conversion, thereby significantly increasing both time and energy costs. Here, we introduce a memristive neural ordinary differential equation (ODE) solver for digital twins, which is capable of capturing continuous-time dynamics and facilitates the modelling of complex systems using an infinite-depth model. By integrating storage and computation within analogue memristor arrays, we circumvent the von Neumann bottleneck, thus enhancing both speed and energy efficiency. We experimentally validate our approach by developing a digital twin of the HP memristor, which accurately extrapolates its nonlinear dynamics, achieving a 4.2-fold projected speedup and a 41.4-fold projected decrease in energy consumption compared to state-of-the-art digital hardware, while maintaining an acceptable error margin. Additionally, we demonstrate scalability through experimentally grounded simulations of Lorenz96 dynamics, exhibiting projected performance improvements of 12.6-fold in speed and 189.7-fold in energy efficiency relative to traditional digital approaches. By harnessing the capabilities of fully analogue computing, our breakthrough accelerates the development of digital twins, offering an efficient and rapid solution to meet the demands of Industry 4.0.