ONNXim: A Fast, Cycle-level Multi-core NPU Simulator
Hyungkyu Ham, Wonhyuk Yang, Yunseon Shin, Okkyun Woo, Guseul Heo,, Sangyeop Lee, Jongse Park, Gwangsun Kim

TL;DR
ONNXim is a high-speed, cycle-level multi-core NPU simulator that efficiently models DRAM, NoC, and multi-tenancy, enabling practical research and design space exploration for DNN serving systems.
Contribution
It introduces a fast, cycle-level multi-core NPU simulator that supports ONNX models and multi-tenancy, overcoming limitations of existing tools.
Findings
Significantly faster than existing simulators (up to 384x)
Supports detailed DRAM and NoC modeling for contention analysis
Enables practical multi-tenant NPU case studies
Abstract
As DNNs are widely adopted in various application domains while demanding increasingly higher compute and memory requirements, designing efficient and performant NPUs (Neural Processing Units) is becoming more important. However, existing architectural NPU simulators lack support for high-speed simulation, multi-core modeling, multi-tenant scenarios, detailed DRAM/NoC modeling, and/or different deep learning frameworks. To address these limitations, this work proposes ONNXim, a fast cycle-level simulator for multi-core NPUs in DNN serving systems. It takes DNN models represented in the ONNX graph format generated from various deep learning frameworks for ease of simulation. In addition, based on the observation that typical NPU cores process tensor tiles from on-chip scratchpad memory with deterministic compute latency, we forgo a detailed modeling for the computation while still…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Simulation Techniques and Applications · Radiation Effects in Electronics
