Hardware Implementation of Soft Mapper/Demappers in Iterative EP-based Receivers

TL;DR

This paper introduces FPGA implementations of an EP-based iterative receiver for various modulation schemes, demonstrating comparable performance to floating-point and efficient resource usage.

Contribution

First FPGA implementation of an EP-based receiver for QPSK, 8-PSK, and 16-QAM with optimized soft mapper/demapper architectures.

Findings

Fixed-point implementation performs comparably to floating-point.

Proposed architecture demonstrates efficient FPGA resource utilization.

Analytical approximations reduce complexity of the receiver.

Abstract

This paper presents a comprehensive study and implementations onto FPGA device of an Expectation Propagation (EP)-based receiver for QPSK, 8-PSK, and 16-QAM. To the best of our knowledge, this is the first for this kind of receiver. The receiver implements a Frequency Domain (FD) Self-Iterated Linear Equalizer (SILE), where EP is used to approximate the true posterior distribution of the transmitted symbols with a simpler distribution. Analytical approximations for the EP feedback generation process and the three constellations are applied to lessen the complexity of the soft mapper/demapper architectures. The simulation results demonstrate that the fixed-point version performs comparably to the floating-point. Moreover, implementation results show the efficiency in terms of FPGA resource usage of the proposed architecture.