Apparate: Evading Memory Hierarchy with GodSpeed Wireless-on-Chip

TL;DR

This paper discusses the integration of wireless-on-chip technology with high-speed DRAM to potentially eliminate traditional memory hierarchies, leading to more efficient and faster computing systems.

Contribution

It introduces the concept of using GodSpeed wireless transceivers on chip to enable direct memory access, challenging conventional memory hierarchy designs.

Findings

Wireless-on-chip can reduce memory access latency.

High-bandwidth DDR and wireless integration enhances system responsiveness.

Potential to eliminate traditional memory hierarchies.

Abstract

The rapid advancements in memory systems, CPU technology, and emerging technologies herald a transformative potential in computing, promising to revolutionize memory hierarchies. Innovations in DDR memory are delivering unprecedented bandwidth, while advancements in on-chip wireless technology are reducing size and increasing speed. The introduction of godspeed wireless transceivers on chip, alongside near high-speed DRAM, is poised to directly facilitate memory requests. This integration suggests the potential for eliminating traditional memory hierarchies, offering a new paradigm in computing efficiency and speed. These developments indicate a near-future where computing systems are significantly more responsive and powerful, leveraging direct, high-speed memory access mechanisms.