A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems

TL;DR

This paper presents a fully open-source, DMA-enhanced Gigabit Ethernet controller designed for mixed-criticality systems, achieving nearly three times the transmission speed of previous architectures and validated through FPGA prototyping.

Contribution

It introduces a novel, performance-optimized open-source Ethernet architecture that overcomes existing limitations and bridges the gap between academic research and industrial applications.

Findings

Packet transmission speed increased by up to 3x

Validated through FPGA implementation in heterogeneous MCSs

Outperforms existing open-source Ethernet architectures

Abstract

The ongoing revolution in application domains targeting autonomous navigation, first and foremost automotive "zonalization", has increased the importance of certain off-chip communication interfaces, particularly Ethernet. The latter will play an essential role in next-generation vehicle architectures as the backbone connecting simultaneously and instantaneously the zonal/domain controllers. There is thereby an incumbent need to introduce a performant Ethernet controller in the open-source HW community, to be used as a proxy for architectural explorations and prototyping of mixed-criticality systems (MCSs). Driven by this trend, in this work, we propose a fully open-source, DMA-enhanced, technology-agnostic Gigabit Ethernet architecture that overcomes the limitations of existing open-source architectures, such as Lowrisc's Ethernet, often tied to FPGA implementation, performance-bound by sub-optimal design choices such as large memory buffers, and in general not mature enough to bridge the gap between academia and industry. Besides the area advantage, the proposed design increases packet transmission speed up to almost 3x compared to Lowrisc's and is validated through implementation and FPGA prototyping into two open-source, heterogeneous MCSs.