Superconducting qubits in the millions: the potential and limitations of modularity

TL;DR

This paper models a modular superconducting qubit architecture for fault-tolerant quantum computing, estimating resources, costs, and limitations to guide future large-scale quantum computer development.

Contribution

It introduces a resource estimation framework and software tool to analyze the physical requirements and trade-offs of modular superconducting quantum architectures.

Findings

Quantifies qubit, power, and time requirements for quantum algorithms.

Identifies architectural bottlenecks and trade-offs in modular quantum systems.

Provides insights into the scalability and limitations of superconducting qubit-based FTQCs.

Abstract

The development of fault-tolerant quantum computers (FTQCs) is receiving increasing attention within the quantum computing community. Like conventional digital computers, FTQCs, which utilize error correction and millions of physical qubits, have the potential to address some of humanity's grand challenges. However, accurate estimates of the tangible scale of future FTQCs, based on transparent assumptions, are uncommon. How many physical qubits are necessary to solve a practical problem intractable for classical hardware? What costs arise from distributing quantum computation across multiple machines? This paper presents an architectural model of a potential FTQC based on superconducting qubits, divided into discrete modules and interconnected via coherent links. We employ a resource estimation framework and software tool to assess the physical resources required to execute specific quantum algorithms compiled into their graph-state form and arranged onto a modular superconducting hardware architecture. Our tool can predict the size, power consumption, and execution time of these algorithms based on explicit assumptions about the system's physical layout, thermal load, and modular connectivity. We assess the resources needed for quantum computation examples that serve as building blocks of proposed applications, quantifying the architectural bottlenecks and trade-offs that remain to be addressed to deliver utility.