LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation

TL;DR

This paper introduces LLANA, a framework that combines Large Language Models with Bayesian Optimization to improve the efficiency and effectiveness of analog layout constraint generation, addressing current limitations in convergence and data requirements.

Contribution

The paper proposes a novel LLANA framework that leverages LLMs to enhance BO for analog layout synthesis, enabling faster convergence and better exploration of design space.

Findings

LLANA achieves performance comparable to state-of-the-art BO methods.

LLANA enables more effective exploration of the analog circuit design space.

Experimental results validate the efficiency and effectiveness of LLANA.

Abstract

Analog layout synthesis faces significant challenges due to its dependence on manual processes, considerable time requirements, and performance instability. Current Bayesian Optimization (BO)-based techniques for analog layout synthesis, despite their potential for automation, suffer from slow convergence and extensive data needs, limiting their practical application. This paper presents the \texttt{LLANA} framework, a novel approach that leverages Large Language Models (LLMs) to enhance BO by exploiting the few-shot learning abilities of LLMs for more efficient generation of analog design-dependent parameter constraints. Experimental results demonstrate that \texttt{LLANA} not only achieves performance comparable to state-of-the-art (SOTA) BO methods but also enables a more effective exploration of the analog circuit design space, thanks to LLM's superior contextual understanding and learning efficiency. The code is available at https://github.com/dekura/LLANA.