PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs

TL;DR

PolyLUT-Add enhances FPGA-based LUT neural networks by combining sub-neurons through addition, significantly reducing LUT resource usage and latency while maintaining accuracy across various benchmarks.

Contribution

It introduces PolyLUT-Add, a novel method for increasing neuron connectivity in LUT networks, along with a scalable architecture for improved FPGA deployment.

Findings

Achieves 2.0-13.9x LUT reduction for similar accuracy.

Reduces latency by 1.2-1.6x.

Effective across multiple benchmarks.

Abstract

FPGAs have distinct advantages as a technology for deploying deep neural networks (DNNs) at the edge. Lookup Table (LUT) based networks, where neurons are directly modeled using LUTs, help maximize this promise of offering ultra-low latency and high area efficiency on FPGAs. Unfortunately, LUT resource usage scales exponentially with the number of inputs to the LUT, restricting PolyLUT to small LUT sizes. This work introduces PolyLUT-Add, a technique that enhances neuron connectivity by combining $A$ PolyLUT sub-neurons via addition to improve accuracy. Moreover, we describe a novel architecture to improve its scalability. We evaluated our implementation over the MNIST, Jet Substructure classification, and Network Intrusion Detection benchmark and found that for similar accuracy, PolyLUT-Add achieves a LUT reduction of $2.0-13.9\times$ with a $1.2-1.6\times$ decrease in latency.