VerilogReader: LLM-Aided Hardware Test Generation

TL;DR

This paper introduces VerilogReader, a novel LLM-based framework that enhances hardware test generation by accurately understanding Verilog code, leading to more effective exploration of code branches compared to random testing.

Contribution

It presents a new LLM-integrated approach for hardware test generation that improves code coverage and introduces prompt engineering techniques to expand LLM understanding.

Findings

Outperforms random testing in code coverage within LLM's comprehension scope.

Demonstrates effectiveness on a custom Verilog benchmark suite.

Shows potential for LLM-assisted hardware verification.

Abstract

Test generation has been a critical and labor-intensive process in hardware design verification. Recently, the emergence of Large Language Model (LLM) with their advanced understanding and inference capabilities, has introduced a novel approach. In this work, we investigate the integration of LLM into the Coverage Directed Test Generation (CDG) process, where the LLM functions as a Verilog Reader. It accurately grasps the code logic, thereby generating stimuli that can reach unexplored code branches. We compare our framework with random testing, using our self-designed Verilog benchmark suite. Experiments demonstrate that our framework outperforms random testing on designs within the LLM's comprehension scope. Our work also proposes prompt engineering optimizations to augment LLM's understanding scope and accuracy.