Reconfigurable FPGA-Based Solvers For Sparse Satellite Control

TL;DR

This paper presents a reconfigurable, power-efficient FPGA implementation of an operator splitting algorithm for satellite control, demonstrating improved stability, performance, and energy efficiency through real hardware testing.

Contribution

It introduces a novel FPGA-based solver with reconfigurable bit-width optimization for satellite control, enhancing system stability and power efficiency.

Findings

Successful FPGA-in-the-loop hardware control of satellite dynamics

Enhanced power efficiency compared to traditional methods

Effective reconfigurable bit-width optimization for stability

Abstract

This paper introduces a novel reconfigurable and power-efficient FPGA (Field-Programmable Gate Array) implementation of an operator splitting algorithm for Non-Terrestial Network's (NTN) relay satellites model predictive orientation control (MPC). Our approach ensures system stability and introduces an innovative reconfigurable bit-width FPGA-based optimization solver. To demonstrate its efficacy, we employ a real FPGA-In-the-Loop hardware setup to control simulated satellite dynamics. Furthermore, we conduct an in-depth comparative analysis, examining various fixed-point configurations to evaluate the combined system's closed-loop performance and power efficiency, providing a holistic understanding of the proposed implementation's advantages.