Low-power Rapid Planar Superconducting Logic Devices

TL;DR

This paper introduces scalable, CMOS-compatible planar RSFQ superconducting logic circuits that significantly reduce power consumption and processing time, offering a promising alternative to traditional superconducting and CMOS technologies for high-performance computing.

Contribution

It demonstrates the design and implementation of planar RSFQ logic circuits with weak-link bridges, achieving superior power efficiency and speed compared to traditional RSFQ and CMOS.

Findings

Power consumption as low as 0.8 nW

Processing time as short as 13 ps

Order of magnitude improvements over traditional RSFQ and CMOS

Abstract

The rapid-pace growing demand for high-performance computation and big-data manipulation entails substantial increase in global power consumption, and challenging thermal management. Thus, there is a need in allocating competitive alternatives for complementary metal-oxide-semiconductor (CMOS) technologies. Superconducting platforms, such as rapid single flux quantum (RSFQ) lack electric resistance and excel in power efficiency and time performance. However, traditional RSFQs require 3D geometry for their Josephson junctions (JJs) imposing a large footprint, and hence preventing device miniaturization and increasing processing time. Here, we demonstrate that RSFQ logic circuits of planar geometry with weak-link bridges are scalable, relatively easy to process and are CMOS-compatible on a Si chip. Universal logic gates, as well as combinational arithmetic circuiting that are based on these devices are demonstrated. The power consumption and processing time of these logic circuits were as low as 0.8 nW and 13 ps, an order of magnitude improvement with respect to the equivalent traditional-RSFQ logic circuits and two orders of magnitude with respect to CMOS. The competitive performance of planar RSFQ logic circuits renders them for promising CMOS substitutes, especially in the supercomputational realm.