Synergistic Dynamical Decoupling and Circuit Design for Enhanced Algorithm Performance on Near-Term Quantum Devices

TL;DR

This paper investigates how combining dynamical decoupling with optimized circuit design can improve the performance and robustness of quantum algorithms on near-term devices, emphasizing hardware and algorithm interplay.

Contribution

It demonstrates the synergistic effects of DD and circuit optimization, providing insights into hardware-aware error mitigation strategies for quantum computing.

Findings

Inverse relationship between DD effectiveness and algorithm performance

Gate directionality and circuit symmetry improve error mitigation

Hardware features significantly influence DD success

Abstract

Dynamical decoupling (DD) is a promising technique for mitigating errors in near-term quantum devices. However, its effectiveness depends on both hardware characteristics and algorithm implementation details. This paper explores the synergistic effects of dynamical decoupling and optimized circuit design in maximizing the performance and robustness of algorithms on near-term quantum devices. By utilizing eight IBM quantum devices, we analyze how hardware features and algorithm design impact the effectiveness of DD for error mitigation. Our analysis takes into account factors such as circuit fidelity, scheduling duration, and hardware-native gate set. We also examine the influence of algorithmic implementation details, including specific gate decompositions, DD sequences, and optimization levels. The results reveal an inverse relationship between the effectiveness of DD and the inherent performance of the algorithm. Furthermore, we emphasize the importance of gate directionality and circuit symmetry in improving performance. This study offers valuable insights for optimizing DD protocols and circuit designs, highlighting the significance of a holistic approach that leverages both hardware features and algorithm design for the high-quality and reliable execution of near-term quantum algorithms.