Fast ML-driven Analog Circuit Layout using Reinforcement Learning and Steiner Trees

TL;DR

This paper introduces a reinforcement learning-based approach combined with Steiner tree methods for rapid and automated analog circuit layout, significantly reducing design time and bridging design and verification processes.

Contribution

It presents a novel AI-driven pipeline that integrates reinforcement learning and Steiner trees for efficient analog circuit layout generation.

Findings

Layout generation runtime reduced to 1.5% of manual effort

Effective automatic placement under topological constraints

Unified framework bridging design and verification

Abstract

This paper presents an artificial intelligence driven methodology to reduce the bottleneck often encountered in the analog ICs layout phase. We frame the floorplanning problem as a Markov Decision Process and leverage reinforcement learning for automatic placement generation under established topological constraints. Consequently, we introduce Steiner tree-based methods for the global routing step and generate guiding paths to be used to connect every circuit block. Finally, by integrating these solutions into a procedural generation framework, we present a unified pipeline that bridges the divide between circuit design and verification steps. Experimental results demonstrate the efficacy in generating complete layouts, eventually reducing runtimes to 1.5% compared to manual efforts.