FPsPIN: An FPGA-based Open-Hardware Research Platform for Processing in the Network

TL;DR

FPsPIN is an open-source FPGA-based platform that enables research on network offloading, demonstrating high overlap ratios in MPI processing and facilitating end-to-end experiments on smart NICs.

Contribution

This work introduces FPsPIN, a full FPGA implementation of sPIN, providing a flexible platform for network offloading research and practical evaluation.

Findings

Achieved 96% overlap ratio in MPI datatype processing

Demonstrated the feasibility of FPGA-based sPIN implementation

Provided an open-source platform for end-to-end NIC experiments

Abstract

In the era of post-Moore computing, network offload emerges as a solution to two challenges: the imperative for low-latency communication and the push towards hardware specialisation. Various methods have been employed to offload protocol- and data-processing onto network interface cards (NICs), from firmware modification to running full Linux on NICs for application execution. The sPIN project enables users to define handlers executed upon packet arrival. While simulations show sPIN's potential across diverse workloads, a full-system evaluation is lacking. This work presents FPsPIN, a full FPGA-based implementation of sPIN. FPsPIN is showcased through offloaded MPI datatype processing, achieving a 96% overlap ratio. FPsPIN provides an adaptable open-source research platform for researchers to conduct end-to-end experiments on smart NICs.