Massive MIMO-ISAC System With 1-Bit ADCs/DACs
Bowen Wang, Hongyu Li, Bin Liao, Ziyang Cheng

TL;DR
This paper proposes a hardware-efficient massive MIMO-ISAC system using 1-bit ADCs/DACs, analyzing its radar and communication performance, and demonstrating its energy efficiency and balanced performance through numerical validation.
Contribution
It introduces a novel 1-bit MIMO-ISAC system with joint transceiver designs and provides analysis and solutions for performance optimization.
Findings
The 1BitISAC system reduces power consumption and hardware costs.
Performance analysis shows effective radar detection and communication quality.
Numerical results validate the system's superiority in energy efficiency and balanced ISAC performance.
Abstract
This paper investigates a hardware-efficient massive multiple-input multiple-output integrated sensing and communication (MIMO-ISAC) system with 1-bit analog-to-digital converters (ADCs)/digital-to-analog converters (DACs). The proposed system, referred to as 1BitISAC, employs 1-bit DACs at the ISAC transmitter and 1-bit ADCs at the sensing receiver, achieving significant reductions in power consumption and hardware costs. For such kind of systems, two 1BitISAC joint transceiver designs, i.e., i) quality of service constrained 1BitISAC design and ii) quality of detection constrained design, are considered and the corresponding problems are formulated. In order to address these problems, we thoroughly analyze the radar detection performance after 1-bit ADCs quantization and the communication bit error rate. This analysis yields new design insights and leads to unique radar and…
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