Single-Event Upset Analysis of a Systolic Array based Deep Neural Network Accelerator

TL;DR

This paper analyzes how single-event upsets affect a systolic array-based DNN accelerator using fault injection simulations, identifying sensitive hardware components and informing mitigation strategies.

Contribution

It provides a detailed, model-agnostic fault sensitivity analysis of a DNN accelerator's hardware blocks through RTL simulation and fault injection.

Findings

Identifies hardware components most vulnerable to SEUs.

Provides fault propagation probabilities for different flip-flop groups.

Suggests optimal mitigation strategies based on sensitivity analysis.

Abstract

Deep Neural Network (DNN) accelerators are extensively used to improve the computational efficiency of DNNs, but are prone to faults through Single-Event Upsets (SEUs). In this work, we present an in-depth analysis of the impact of SEUs on a Systolic Array (SA) based DNN accelerator. A fault injection campaign is performed through a Register-Transfer Level (RTL) based simulation environment to improve the observability of each hardware block, including the SA itself as well as the post-processing pipeline. From this analysis, we present the sensitivity, independent of a DNN model architecture, for various flip-flop groups both in terms of fault propagation probability and fault magnitude. This allows us to draw detailed conclusions and determine optimal mitigation strategies.