Full-stack evaluation of Machine Learning inference workloads for RISC-V systems

TL;DR

This paper evaluates the performance of machine learning inference workloads on RISC-V architectures using gem5, highlighting current simulation limitations and proposing a comprehensive benchmarking approach with an open-source compilation toolchain.

Contribution

It provides a full-stack evaluation framework for ML workloads on RISC-V, combining gem5 simulation with MLIR-based compilation, and identifies key limitations for future improvements.

Findings

Benchmarking results for deep learning inference on RISC-V

Identification of gem5 simulation limitations

Insights for future RISC-V architectural development

Abstract

Architectural simulators hold a vital role in RISC-V research, providing a crucial platform for workload evaluation without the need for costly physical prototypes. They serve as a dynamic environment for exploring innovative architectural concepts, enabling swift iteration and thorough analysis of performance metrics. As deep learning algorithms become increasingly pervasive, it is essential to benchmark new architectures with machine learning workloads. The diverse computational kernels used in deep learning algorithms highlight the necessity for a comprehensive compilation toolchain to map to target hardware platforms. This study evaluates the performance of a wide array of machine learning workloads on RISC-V architectures using gem5, an open-source architectural simulator. Leveraging an open-source compilation toolchain based on Multi-Level Intermediate Representation (MLIR), the research presents benchmarking results specifically focused on deep learning inference workloads. Additionally, the study sheds light on current limitations of gem5 when simulating RISC-V architectures, offering insights for future development and refinement.