Analog or Digital In-memory Computing? Benchmarking through Quantitative Modeling

TL;DR

This paper presents a quantitative performance model comparing analog and digital in-memory computing architectures, revealing their relative strengths and energy efficiencies across different workloads and configurations.

Contribution

It introduces an analytical performance model validated against real implementations, enabling comprehensive system-level comparison of AIMC and DIMC architectures.

Findings

DIMC has higher computational density than AIMC.

AIMC with large macros can be more energy-efficient on certain layers.

DIMC with small macros outperforms AIMC on depthwise-layers.

Abstract

In-Memory Computing (IMC) has emerged as a promising paradigm for energy-efficient, throughput-efficient and area-efficient machine learning at the edge. However, the differences in hardware architectures, array dimensions, and fabrication technologies among published IMC realizations have made it difficult to grasp their relative strengths. Moreover, previous studies have primarily focused on exploring and benchmarking the peak performance of a single IMC macro rather than full system performance on real workloads. This paper aims to address the lack of a quantitative comparison of Analog In-Memory Computing (AIMC) and Digital In-Memory Computing (DIMC) processor architectures. We propose an analytical IMC performance model that is validated against published implementations and integrated into a system-level exploration framework for comprehensive performance assessments on different workloads with varying IMC configurations. Our experiments show that while DIMC generally has higher computational density than AIMC, AIMC with large macro sizes may have better energy efficiency than DIMC on convolutional-layers and pointwise-layers, which can exploit high spatial unrolling. On the other hand, DIMC with small macro size outperforms AIMC on depthwise-layers, which feature limited spatial unrolling opportunities inside a macro.