Low-Energy Line Codes for On-Chip Networks

TL;DR

This paper introduces Low-Energy Line Codes (LELCs) that significantly reduce on-chip network energy consumption by minimizing voltage transitions, offering new energy-efficient communication strategies for processor design.

Contribution

The paper proposes a novel line coding scheme, LELCs, specifically designed to lower on-chip network energy use by reducing link voltage transitions, with adaptable energy-performance trade-offs.

Findings

LELCs reduce link energy consumption significantly.

LELCs maintain acceptable performance levels.

Energy savings depend on coding parameters.

Abstract

Energy is a primary constraint in processor design, and much of that energy is consumed in on-chip communication. Communication can be intra-core (e.g., from a register file to an ALU) or inter-core (e.g., over the on-chip network). In this paper, we use the on-chip network (OCN) as a case study for saving on-chip communication energy. We have identified a new way to reduce the OCN's link energy consumption by using line coding, a longstanding technique in information theory. Our line codes, called Low-Energy Line Codes (LELCs), reduce energy by reducing the frequency of voltage transitions of the links, and they achieve a range of energy/performance trade-offs.