Fully parallel implementation of digital memcomputing on FPGA

TL;DR

This paper introduces a fully parallel FPGA implementation of digital memcomputing that significantly accelerates solving complex SAT problems by reducing scaling and execution time compared to traditional methods.

Contribution

The authors developed a novel FPGA-based digital memcomputing solver using integer arithmetic, achieving high-speed parallel solution of difficult SAT instances.

Findings

Execution time per step is 96 ns.

Reduced scaling exponent by about 1 compared to sequential C++.

Achieved approximately 1000x faster solutions than C++ code.

Abstract

We present a fully parallel digital memcomputing solver implemented on a field-programmable gate array (FPGA) board. For this purpose, we have designed an FPGA code that solves the ordinary differential equations associated with digital memcomputing in parallel. A feature of the code is the use of only integer-type variables and integer constants to enhance optimization. Consequently, each integration step in our solver is executed in 96~ns. This method was utilized for difficult instances of the Boolean satisfiability (SAT) problem close to a phase transition, involving up to about 150 variables. Our results demonstrate that the parallel implementation reduces the scaling exponent by about 1 compared to a sequential C++ code on a standard computer. Additionally, compared to C++ code, we observed a time-to-solution advantage of about three orders of magnitude. Given the limitations of FPGA resources, the current implementation of digital memcomputing will be especially useful for solving compact but challenging problems.