Time-Series Forecasting and Sequence Learning Using Memristor-based Reservoir System

TL;DR

This paper presents a memristor-based reservoir computing system for efficient, in-situ time-series forecasting on edge devices, achieving high energy efficiency and robustness with minimal performance loss.

Contribution

The work introduces a novel memristor-based echo state network accelerator that enables efficient online learning and temporal data processing on resource-constrained devices.

Findings

Achieves 247X reduction in energy consumption compared to CMOS digital design.

Maintains performance with marginal degradation due to memristor device limitations.

Demonstrates robustness to device failures below 10%.

Abstract

Pushing the frontiers of time-series information processing in the ever-growing domain of edge devices with stringent resources has been impeded by the systems' ability to process information and learn locally on the device. Local processing and learning of time-series information typically demand intensive computations and massive storage as the process involves retrieving information and tuning hundreds of parameters back in time. In this work, we developed a memristor-based echo state network accelerator that features efficient temporal data processing and in-situ online learning. The proposed design is benchmarked using various datasets involving real-world tasks, such as forecasting the load energy consumption and weather conditions. The experimental results illustrate that the hardware model experiences a marginal degradation in performance as compared to the software counterpart. This is mainly attributed to the limited precision and dynamic range of network parameters when emulated using memristor devices. The proposed system is evaluated for lifespan, robustness, and energy-delay product. It is observed that the system demonstrates reasonable robustness for device failure below 10%, which may occur due to stuck-at faults. Furthermore, 247X reduction in energy consumption is achieved when compared to a custom CMOS digital design implemented at the same technology node.