CMOS-compatible Strain Engineering for High-Performance Monolayer Semiconductor Transistors

TL;DR

This paper demonstrates a CMOS-compatible method using silicon nitride capping layers to impart strain on monolayer MoS2 transistors, significantly boosting their electrical performance and enabling high current densities at nanoscale dimensions.

Contribution

It introduces a low-temperature, CMOS-compatible strain engineering technique for 2D transistors that enhances performance and surpasses previous current density benchmarks.

Findings

Strain increases on-state current by up to 60%.

Performance improvements are maximized at ~200 nm device dimensions.

Simulations show tensile strain reduces contact Schottky barriers.

Abstract

Strain engineering has played a key role in modern silicon electronics, having been introduced as a mobility booster in the 1990s and commercialized in the early 2000s. Achieving similar advances with two-dimensional (2D) semiconductors in a CMOS (complementary metal oxide semiconductor) compatible manner would radically improve the industrial viability of 2D transistors. Here, we show silicon nitride capping layers can impart strain to monolayer MoS2 transistors on conventional silicon substrates, enhancing their electrical performance with a low thermal budget (350 {\deg}C), CMOS-compatible approach. Strained back-gated and dual-gated MoS2 transistors demonstrate median increases up to 60% and 45% in on-state current, respectively. The greatest improvements are found when both transistor channels and contacts are reduced to ~200 nm, reaching saturation currents of 488 uA/um, higher than any previous reports at such short contact pitch. Simulations reveal that most benefits arise from tensile strain lowering the contact Schottky barriers, and that further reducing device dimensions (including contacts) will continue to offer increased strain and performance improvements.