Efficient and Scalable Architectures for Multi-Level Superconducting Qubit Readout
Chaithanya Naik Mude, Satvik Maurya, Benjamin Lienhard, Swamit Tannu

TL;DR
This paper introduces a scalable, high-fidelity three-level readout protocol for superconducting qubits that reduces hardware resources and readout time, improving leakage detection and quantum error correction.
Contribution
The authors develop a novel multi-level readout method combining matched filters and neural networks, significantly reducing hardware complexity and enhancing real-time leakage detection.
Findings
Reduces FPGA resource usage by 60x
Decreases readout time by 20%
Achieves 6.6% higher readout accuracy
Abstract
Realizing the full potential of quantum computing requires large-scale quantum computers capable of running quantum error correction (QEC) to mitigate hardware errors and maintain quantum data coherence. While quantum computers operate within a two-level computational subspace, many processor modalities are inherently multi-level systems. This leads to occasional leakage into energy levels outside the computational subspace, complicating error detection and undermining QEC protocols. The problem is particularly severe in engineered qubit devices like superconducting transmons, a leading technology for fault-tolerant quantum computing. Addressing this challenge requires effective multi-level quantum system readout to identify and mitigate leakage errors. We propose a scalable, high-fidelity three-level readout that reduces FPGA resource usage by compared to the baseline while…
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Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Quantum Information and Cryptography · Neural Networks and Reservoir Computing
