Development and optimization of large-scale integration of 2D material in memristors

TL;DR

This paper develops and compares two CMOS-compatible protocols for large-scale integration of MoS₂-based memristors, demonstrating improved electrical performance and reproducibility by optimizing transfer and contamination removal processes.

Contribution

It introduces two novel fabrication protocols for MoS₂ memristors, highlighting the importance of contamination control for enhanced device performance.

Findings

Contamination removal improves electrical switching performance.

The second protocol yields better reproducibility.

Switching mechanism involves conduction through grain boundaries.

Abstract

Two-dimensional (2D) materials like transition metal dichalcogenides (TMD) have proved to be serious candidates to replace silicon in several technologies with enhanced performances. In this respect, the two remaining challenges are the wafer scale growth of TMDs and their integration into operational devices using clean room compatible processes. In this work, two different CMOS-compatible protocols are developed for the fabrication of MoS$_2$-based memristors, and the resulting performances are compared. The quality of MoS$_2$ at each stage of the process is characterized by Raman spectroscopy and x-ray photoemission spectroscopy. In the first protocol, the structure of MoS$_2$ is preserved during transfer and patterning processes. However, a polymer layer with a minimum thickness of 3 nm remains at the surface of MoS$_2$ limiting the electrical switching performances. In the second protocol, the contamination layer is completely removed resulting in improved electrical switching performances and reproducibility. Based on physico-chemical and electrical results, the switching mechanism is discussed in terms of conduction through grain boundaries.