TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
Fangzhou Wang, Qijing Wang, Lilas Alrahis, Bangqi Fu, Shui Jiang,, Xiaopeng Zhang, Ozgur Sinanoglu, Tsung-Yi Ho, Evangeline F.Y. Young, Johann, Knechtel

TL;DR
TroLLoc introduces a novel integrated approach combining logic locking and layout hardening to proactively secure IC layouts against hardware Trojan insertion, demonstrating effectiveness and robustness with manageable overheads.
Contribution
This work is the first to unify logic locking and layout hardening for IC security closure, integrated into a commercial design flow and validated against recent security benchmarks.
Findings
Successfully resists Trojan insertion in ISPD benchmarks
Maintains effectiveness against machine learning-based attacks
Operates with reasonable design overheads
Abstract
Due to cost benefits, supply chains of integrated circuits (ICs) are largely outsourced nowadays. However, passing ICs through various third-party providers gives rise to many security threats, like piracy of IC intellectual property or insertion of hardware Trojans, i.e., malicious circuit modifications. In this work, we proactively and systematically protect the physical layouts of ICs against post-design insertion of Trojans. Toward that end, we propose TroLLoc, a novel scheme for IC security closure that employs, for the first time, logic locking and layout hardening in unison. TroLLoc is fully integrated into a commercial-grade design flow, and TroLLoc is shown to be effective, efficient, and robust. Our work provides in-depth layout and security analysis considering the challenging benchmarks of the ISPD'22/23 contests for security closure. We show that TroLLoc successfully…
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Taxonomy
TopicsPhysical Unclonable Functions (PUFs) and Hardware Security · Integrated Circuits and Semiconductor Failure Analysis · VLSI and Analog Circuit Testing
