Investigating impact of bit-flip errors in control electronics on quantum computation

TL;DR

This study examines how bit-flip errors in FPGA control electronics affect quantum gate fidelity, demonstrating significant deviations caused by errors and proposing a simple error correction method that mitigates these effects with minimal overhead.

Contribution

The paper identifies the impact of bit-flip faults in FPGA memories on quantum gate operations and introduces a 3-bit repetition error correction code to reduce errors effectively.

Findings

Bit flips in amplitude exponent and initial mantissa cause up to 200% TVD increase.

Remaining bits show natural tolerance to errors.

Proposed 3-bit repetition code reduces TVD increase to below 40%.

Abstract

In this paper, we investigate the impact of bit flip errors in FPGA memories in control electronics on quantum computing systems. FPGA memories are integral in storing the amplitude and phase information pulse envelopes, which are essential for generating quantum gate pulses. However, these memories can incur faults due to physical and environmental stressors such as electromagnetic interference, power fluctuations, and temperature variations and adversarial fault injections, potentially leading to errors in quantum gate operations. To understand how these faults affect quantum computations, we conducted a series of experiments to introduce bit flips into the amplitude (both real and imaginary components) and phase values of quantum pulses using IBM's simulated quantum environments, FakeValencia, FakeManila, and FakeLima. Our findings reveal that bit flips in the exponent and initial mantissa bits of the real amplitude cause substantial deviations in quantum gate operations, with TVD increases as high as ~200%. Interestingly, the remaining bits exhibited natural tolerance to errors. We proposed a 3-bit repetition error correction code, which effectively reduced the TVD increases to below 40% without incurring any memory overhead. Due to reuse of less significant bits for error correction, the proposed approach introduces maximum of 5-7% extra TVD in nominal cases. However, this can be avoided by sacrificing memory area for implementing the repetition code.