PARSAC: Fast, Human-quality Floorplanning for Modern SoCs with Complex Design Constraints
Hesham Mostafa, Uday Mallappa, Mikhail Galkin, Mariano Phielipp,, Somdeb Majumdar

TL;DR
PARSAC is a parallel, constraint-aware floorplanning tool for modern SoCs that significantly improves solution quality and speed over traditional simulated annealing methods, especially when hard placement constraints are involved.
Contribution
The paper introduces PARSAC, a novel parallel floorplanning tool that incorporates hard constraints effectively, outperforming existing methods in speed and solution quality.
Findings
PARSAC outperforms traditional SA in constrained floorplanning tasks.
PARSAC constructs Pareto-optimal solutions quickly.
The method is open-source for community use and development.
Abstract
The floorplanning of Systems-on-a-Chip (SoCs) and of chip sub-systems is a crucial step in the physical design flow as it determines the optimal shapes and locations of the blocks that make up the system. Simulated Annealing (SA) has been the method of choice for tackling classical floorplanning problems where the objective is to minimize wire-length and the total placement area. The goal in industry-relevant floorplanning problems, however, is not only to minimize area and wire-length, but to do that while respecting hard placement constraints that specify the general area and/or the specific locations for the placement of some blocks. We show that simply incorporating these constraints into the SA objective function leads to sub-optimal, and often illegal, solutions. We propose the Constraints-Aware Simulated Annealing (CA-SA) method and show that it strongly outperforms vanilla SA in…
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Taxonomy
TopicsVLSI and FPGA Design Techniques · VLSI and Analog Circuit Testing · Embedded Systems Design Techniques
