Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?

TL;DR

This paper demonstrates that an enhanced open-source EDA flow can successfully design a multi-million-gate Linux-booting RV64 SoC, achieving significant improvements in performance, area, and efficiency, proving open-source tools are viable for complex chip design.

Contribution

The paper introduces enhancements to the open-source Yosys+Openroad flow, including new synthesis tools, interfaces, and macro-operators, enabling the design of a competitive multi-million-gate SoC.

Findings

Achieved 77 MHz operating frequency on a 130 nm SoC

Reduced logic area by 1.6x compared to baseline

Decreased tool runtime by 2.5x and peak RAM usage by 2.9x

Abstract

Designing complex, multi-million-gate application-specific integrated circuits requires robust and mature electronic design automation (EDA) tools. We describe our efforts in enhancing the open-source Yosys+Openroad EDA flow to implement Basilisk, a fully open-source, Linux-booting RV64GC system-on-chip (SoC) design. We analyze the quality-of-results impact of our enhancements to synthesis tools, interfaces between EDA tools, logic optimization scripts, and a newly open-sourced library of optimized arithmetic macro-operators. We also introduce a streamlined physical design flow with an improved power grid and cell placement integration. Our Basilisk SoC design was taped out in IHP's open 130 nm technology. It achieves an operating frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3x improvement compared to the baseline open-source EDA flow, while also reducing logic area by 1.6x. Furthermore, tool runtime was reduced by 2.5x, and peak RAM usage decreased by 2.9x. Through collaboration with EDA tool developers and domain experts, Basilisk establishes solid "proof of existence" for a fully open-source EDA flow used in designing a competitive multi-million-gate digital SoC.