Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC

TL;DR

Basilisk demonstrates a significant advancement in open-source EDA tools by optimizing an ASIC design flow for a RISC-V SoC, achieving higher performance and core utilization on an open-source Linux-capable platform.

Contribution

The paper introduces Basilisk, an enhanced open-source ASIC design flow with improved synthesis, logic optimization, and physical design, enabling competitive performance on a RISC-V SoC.

Findings

Achieves 77 MHz operation frequency, 2.3x improvement over baseline.

Increases core utilization to 55% from 50%.

Demonstrates effective collaboration with EDA developers.

Abstract

We introduce Basilisk, an optimized application-specific integrated circuit (ASIC) implementation and design flow building on the end-to-end open-source Iguana system-on-chip (SoC). We present enhancements to synthesis tools and logic optimization scripts improving quality of results (QoR), as well as an optimized physical design with an improved power grid and cell placement integration enabling a higher core utilization. The tapeout-ready version of Basilisk implemented in IHP's open 130 nm technology achieves an operation frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3x improvement compared to the baseline open-source EDA design flow presented in Iguana, and a higher 55 % core utilization compared to 50 % in the baseline design. Through collaboration with EDA tool developers and domain experts, Basilisk exemplifies a synergistic effort towards competitive open-source electronic design automation (EDA) tools for research and industry applications.