Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT

TL;DR

This paper demonstrates how large language models like ChatGPT can generate Verilog code for recurrent spiking neural networks, validate them on FPGA hardware, and synthesize them using open-source EDA tools, bridging AI and hardware design.

Contribution

It introduces a novel approach of using LLMs and natural language prompts to automatically generate and validate hardware description code for neural networks.

Findings

Successfully generated Verilog code for neural networks using ChatGPT4.

Validated the design on FPGA hardware and in open-source EDA flow.

Achieved synthesis in SkyWater 130 nm technology.

Abstract

This paper investigates the use of Large Language Models (LLMs) and natural language prompts to generate hardware description code, namely Verilog. Building on our prior work, we employ OpenAI's ChatGPT4 and natural language prompts to synthesize an RTL Verilog module of a programmable recurrent spiking neural network, while also generating test benches to assess the system's correctness. The resultant design was validated in three simple machine learning tasks, the exclusive OR, the IRIS flower classification and the MNIST hand-written digit classification. Furthermore, the design was validated on a Field-Programmable Gate Array (FPGA) and subsequently synthesized in the SkyWater 130 nm technology by using an open-source electronic design automation flow. The design was submitted to Efabless Tiny Tapeout 6.