Ferroelectrically-enhanced Schottky barrier transistors for Logic-in-Memory applications
Daniele Nazzari, Lukas Wind, Masiar Sistani, Dominik Mayr, Kihye Kim,, Walter M. Weber

TL;DR
This paper explores ferroelectric Hf0.5Zr0.5O2 integration into Schottky-Barrier FETs to enable memory functionalities and multi-level switching, advancing low-power logic-in-memory hardware for neural network applications.
Contribution
It demonstrates ferroelectric polarization control of Schottky barriers in SBFETs, enabling multi-level, stable, low-power memory states for logic-in-memory architectures.
Findings
HZO polarization modulates Schottky barrier heights
Multiple current levels achieved and retained
Potential for low-power neural network hardware
Abstract
Artificial neural networks (ANNs) have had an enormous impact on a multitude of sectors, from research to industry, generating an unprecedented demand for tailor-suited hardware platforms. Their training and execution is highly memory-intensive, clearly evidencing the limitations affecting the currently available hardware based on the von Neumann architecture, which requires frequent data shuttling due to the physical separation of logic and memory units. This does not only limit the achievable performances but also greatly increases the energy consumption, hindering the integration of ANNs into low-power platforms. New Logic in Memory (LiM) architectures, able to unify memory and logic functionalities into a single component, are highly promising for overcoming these limitations, by drastically reducing the need of data transfers. Recently, it has been shown that a very flexible…
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Taxonomy
TopicsSemiconductor materials and devices · Ferroelectric and Negative Capacitance Devices · Advancements in Semiconductor Devices and Circuit Design
