PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC

TL;DR

This paper presents an open-source deployment pipeline for few-shot learning on FPGA SoCs, enabling low-power, low-latency object classification suitable for embedded applications.

Contribution

It introduces an end-to-end pipeline built on Tensil for designing, training, and deploying few-shot learning models on FPGA SoCs, demonstrated with a MiniImageNet classifier.

Findings

Achieved 30 ms latency on PYNQ-Z1 board

Power consumption of 6.2 W

Successful deployment of low-power, low-latency classifier

Abstract

This paper tackles the challenges of implementing few-shot learning on embedded systems, specifically FPGA SoCs, a vital approach for adapting to diverse classification tasks, especially when the costs of data acquisition or labeling prove to be prohibitively high. Our contributions encompass the development of an end-to-end open-source pipeline for a few-shot learning platform for object classification on a FPGA SoCs. The pipeline is built on top of the Tensil open-source framework, facilitating the design, training, evaluation, and deployment of DNN backbones tailored for few-shot learning. Additionally, we showcase our work's potential by building and deploying a low-power, low-latency demonstrator trained on the MiniImageNet dataset with a dataflow architecture. The proposed system has a latency of 30 ms while consuming 6.2 W on the PYNQ-Z1 board.