Controller Synthesis in Timed B\"uchi Automata: Robustness and Punctual Guards

TL;DR

This paper addresses controller synthesis in timed automata with B"uchi objectives, introducing robustness to small perturbations and allowing punctual guards, while maintaining PSPACE complexity.

Contribution

It generalizes existing characterizations to include punctual guards under robustness, with a new structural property on the region abstraction.

Findings

Robust controller synthesis remains in PSPACE.

Punctual guards can be incorporated with a new structural condition.

The approach generalizes previous cycle characterizations to the punctual setting.

Abstract

We consider the synthesis problem on timed automata with B\"uchi objectives, where delay choices made by a controller are subjected to small perturbations. Usually, the controller needs to avoid punctual guards, such as testing the equality of a clock to a constant. In this work, we generalize to a robustness setting that allows for punctual transitions in the automaton to be taken by controller with no perturbation. In order to characterize cycles that resist perturbations in our setting, we introduce a new structural requirement on the reachability relation along an accepting cycle of the automaton. This property is formulated on the region abstraction, and generalizes the existing characterization of winning cycles in the absence of punctual guards. We show that the problem remains within PSPACE despite the presence of punctual guards.