Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical Design
Aman Kumar

TL;DR
This paper presents a pragmatic formal verification approach for complex sequential ECCs in safety-critical systems, employing various reduction techniques to achieve unbounded proofs within 24 hours.
Contribution
The paper introduces a set of complexity reduction techniques and practical strategies for formal verification of sequential ECCs, enabling efficient and confident sign-off.
Findings
Achieved unbounded proof within 24 hours for complex ECCs.
Reduced verification complexity using linearity and abstract models.
Validated approach on safety-critical automotive ECC designs.
Abstract
Error Detection and Correction Codes (ECCs) are often used in digital designs to protect data integrity. Especially in safety-critical systems such as automotive electronics, ECCs are widely used and the verification of such complex logic becomes more critical considering the ISO 26262 safety standards. Exhaustive verification of ECC using formal methods has been a challenge given the high number of data bits to protect. As an example, for an ECC of 128 data bits with a possibility to detect up to four-bit errors, the combination of bit errors is given by 128C1 + 128C2 + 128C3 + 128C4 = 1.1 * 10^7. This vast analysis space often leads to bounded proof results. Moreover, the complexity and state-space increase further if the ECC has sequential encoding and decoding stages. To overcome such problems and sign-off the design with confidence within reasonable proof time, we present a…
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Taxonomy
TopicsManufacturing Process and Optimization · Probabilistic and Robust Engineering Design · Safety Systems Engineering in Autonomy
