Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout

TL;DR

This paper demonstrates the design, fabrication, and testing of embedded FPGAs in 130nm and 28nm CMOS for machine learning tasks in particle detector readout, enabling efficient, reconfigurable data processing at the sensor level.

Contribution

It introduces an open-source framework for designing eFPGAs in advanced CMOS nodes and validates their use for machine learning in collider detector applications.

Findings

Successful fabrication and testing of eFPGAs in 130nm and 28nm CMOS.

Implementation of a machine learning classifier on eFPGA with perfect accuracy.

Proof-of-concept for real-time data reduction in particle detectors.

Abstract

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called "FABulous" was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Further development of the eFPGA technology and its application to collider detector readout is discussed.