Towards Scalable Multi-Chip Wireless Networks with Near-Field Time Reversal

TL;DR

This paper demonstrates that near-field Time Reversal can significantly enhance multi-chip wireless communication speeds by mitigating interference, enabling multiple high-speed links, and achieving over 100 Gb/s in chip-scale networks.

Contribution

It introduces the application of near-field Time Reversal for scalable multi-chip wireless networks, showing its effectiveness in increasing symbol rates and reducing interference.

Findings

Time Reversal increases symbol rate by an order of magnitude.

TR enables multiple concurrent high-speed wireless links.

Achieves aggregate speeds exceeding 100 Gb/s.

Abstract

The concept of Wireless Network-on-Chip (WNoC) has emerged as a potential solution to address the escalating communication demands of modern computing systems due to its low-latency, versatility, and reconfigurability. However, for WNoC to fulfill its potential, it is essential to establish multiple high-speed wireless links across chips. Unfortunately, the compact and enclosed nature of computing packages introduces significant challenges in the form of Co-Channel Interference (CCI) and Inter-Symbol Interference (ISI), which not only hinder the deployment of multiple spatial channels, but also severely restrict the symbol rate of each individual channel. In this paper, we posit that Time Reversal (TR) could be effective in addressing both impairments in this static scenario, thanks to its spatiotemporal focusing capabilities even in the near-field. Through comprehensive full-wave simulations and bit error rate analysis in multiple chip layouts with multiple frequency bands, we provide evidence that TR can increase the symbol rate by an order of magnitude, enabling the deployment of multiple concurrent links and achieving aggregate speeds exceeding 100 Gb/s. Finally, we evaluate the impact of reducing the sampling rate of the TR filter on the achievable speeds, paving the way to practical TR-based wireless communications at the chip scale.