Synchronized Stepwise Control of Firing and Learning Thresholds in a Spiking Randomly Connected Neural Network toward Hardware Implementation

TL;DR

This paper introduces a hardware-friendly spiking neural network model with synchronized, stepwise control of firing and learning thresholds, enhancing temporal data processing and anomaly detection capabilities.

Contribution

It presents a novel hardware-oriented model of intrinsic and synaptic plasticity with synchronized thresholds for improved RNN performance and hardware implementation.

Findings

Effective temporal data learning demonstrated with electrocardiogram data

Threshold discretization enables binary parameters, simplifying hardware design

Self-organization mitigates performance degradation in random RNNs

Abstract

We propose hardware-oriented models of intrinsic plasticity (IP) and synaptic plasticity (SP) for spiking randomly connected recursive neural network (RNN). Although the potential of RNNs for temporal data processing has been demonstrated, randomness of the network architecture often causes performance degradation. Self-organization mechanism using IP and SP can mitigate the degradation, therefore, we compile these functions in a spiking neuronal model. To implement the function of IP, a variable firing threshold is introduced to each excitatory neuron in the RNN that changes stepwise in accordance with its activity. We also define other thresholds for SP that synchronize with the firing threshold, which determine the direction of stepwise synaptic update that is executed on receiving a pre-synaptic spike. We demonstrate the effectiveness of our model through simulations of temporal data learning and anomaly detection with a spiking RNN using publicly available electrocardiograms. Considering hardware implementation, we employ discretized thresholds and synaptic weights and show that these parameters can be reduced to binary if the RNN architecture is appropriately designed. This contributes to minimization of the circuit of the neuronal system having IP and SP.