Evolutionary Large Language Models for Hardware Security: A Comparative Survey

TL;DR

This paper surveys the use of Large Language Models in automating hardware security vulnerability detection and mitigation during the design phase, emphasizing their potential and challenges.

Contribution

It provides a comparative analysis of LLM methodologies for hardware security, highlighting future research directions and the integration of domain-specific knowledge.

Findings

LLMs can autonomously resolve security vulnerabilities in HW designs

Comparison of methodologies reveals scalability and interpretability challenges

Identifies future research areas for specialized LLM architectures

Abstract

Automating hardware (HW) security vulnerability detection and mitigation during the design phase is imperative for two reasons: (i) It must be before chip fabrication, as post-fabrication fixes can be costly or even impractical; (ii) The size and complexity of modern HW raise concerns about unknown vulnerabilities compromising CIA triad. While Large Language Models (LLMs) can revolutionize both HW design and testing processes, within the semiconductor context, LLMs can be harnessed to automatically rectify security-relevant vulnerabilities inherent in HW designs. This study explores the seeds of LLM integration in register transfer level (RTL) designs, focusing on their capacity for autonomously resolving security-related vulnerabilities. The analysis involves comparing methodologies, assessing scalability, interpretability, and identifying future research directions. Potential areas for exploration include developing specialized LLM architectures for HW security tasks and enhancing model performance with domain-specific knowledge, leading to reliable automated security measurement and risk mitigation associated with HW vulnerabilities.