Impact of Top SiO2 interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure
Tao Hu, Xianzhou Shao, Mingkai Bai, Xinpei Jia, Saifei Dai, Xiaoqing, Sun, Runhao Han, Jia Yang, Xiaoyu Ke, Fengbin Tian, Shuai Yang, Junshuai, Chai, Hao Xu, Xiaolei Wang, Wenwu Wang, and Tianchun Ye
TL;DR
This study investigates how varying the top SiO2 interlayer thickness affects the memory window in Si channel FeFET devices with a specific gate structure, revealing that thicker SiO2 increases the window but reduces endurance.
Contribution
It demonstrates the relationship between top SiO2 thickness and memory window size, providing insights for optimizing FeFET performance.
Findings
Memory window increases with thicker top SiO2
Achieved 6.3 V memory window with 3.4 nm SiO2
Endurance degrades as initial memory window increases
Abstract
We study the impact of top SiO2 interlayer thickness on memory window of Si channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. The memory window increases with thicker top SiO2. We realize the memory window of 6.3 V for 3.4 nm top SiO2. Moreover, we find that the endurance characteristic degrades with increasing the initial memory window.
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Taxonomy
TopicsFerroelectric and Negative Capacitance Devices · Semiconductor materials and devices · Semiconductor materials and interfaces