A high-level synthesis approach for precisely-timed, energy-efficient embedded systems
Yuchao Liao, Tosiron Adegbija, Roman Lysecky

TL;DR
This paper introduces a hybrid high-level synthesis framework that explicitly incorporates precise timing specifications into the design of energy-efficient, application-specific embedded systems, demonstrated through various case studies.
Contribution
It presents a novel hybrid HLS approach combining SB-HLS and PD-HLS to support precise timing in embedded system design, improving energy and area efficiency.
Findings
H-HLS achieves low energy and area under timing constraints.
Case studies validate the effectiveness of the approach.
Comparison of PD-HLS tools shows design space benefits.
Abstract
Embedded systems continue to rapidly proliferate in diverse fields, including medical devices, autonomous vehicles, and more generally, the Internet of Things (IoT). Many embedded systems require application-specific hardware components to meet precise timing requirements within limited resource (area and energy) constraints. High-level synthesis (HLS) is an increasingly popular approach for improving the productivity of designing hardware and reducing the time/cost by using high-level languages to specify computational functionality and automatically generate hardware implementations. However, current HLS methods provide limited or no support to incorporate or utilize precise timing specifications within the synthesis and optimization process. In this paper, we present a hybrid high-level synthesis (H-HLS) framework that integrates state-based high-level synthesis (SB-HLS) with…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
