TDRAM: Tag-enhanced DRAM for Efficient Caching
Maryam Babaie, Ayaz Akram, Wendy Elsasser, Brent Haukness, Michael, Miller, Taeksang Song, Thomas Vogelsang, Steven Woo, Jason Lowe-Power

TL;DR
TDRAM introduces a tag-enhanced DRAM cache architecture that significantly reduces latency and energy consumption by enabling fast parallel tag/data access and early tag probing, improving HPC workload performance.
Contribution
The paper presents TDRAM, a novel DRAM microarchitecture with on-die tags and metadata, enabling SRAM-like cache efficiency in DRAM-based caches.
Findings
2.6× faster tag check
1.2× overall speedup
21% energy reduction
Abstract
As SRAM-based caches are hitting a scaling wall, manufacturers are integrating DRAM-based caches into system designs to continue increasing cache sizes. While DRAM caches can improve the performance of memory systems, existing DRAM cache designs suffer from high miss penalties, wasted data movement, and interference between misses and demand requests. In this paper, we propose TDRAM, a novel DRAM microarchitecture tailored for caching. TDRAM enhances HBM3 by adding a set of small low-latency mats to store tags and metadata on the same die as the data mats. These mats enable fast parallel tag and data access, on-DRAM-die tag comparison, and conditional data response based on comparison result (reducing wasted data transfers) akin to SRAM caches mechanism. TDRAM further optimizes the hit and miss latencies by performing opportunistic early tag probing. Moreover, TDRAM introduces a flush…
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Taxonomy
TopicsCaching and Content Delivery · Advanced Data Storage Technologies · Network Packet Processing and Optimization
