KATO: Knowledge Alignment and Transfer for Transistor Sizing of Different Design and Technology

TL;DR

KATO introduces a transfer learning-enhanced Bayesian optimization method for transistor sizing that effectively transfers knowledge across different circuits and technology nodes, significantly reducing simulation efforts and improving design outcomes.

Contribution

It presents the first transfer learning approach for Bayesian optimization in transistor sizing, including efficient kernel construction and a selective transfer scheme.

Findings

Up to 2x reduction in simulation efforts

1.2x improvement in design quality

Effective knowledge transfer across circuits and technology nodes

Abstract

Automatic transistor sizing in circuit design continues to be a formidable challenge. Despite that Bayesian optimization (BO) has achieved significant success, it is circuit-specific, limiting the accumulation and transfer of design knowledge for broader applications. This paper proposes (1) efficient automatic kernel construction, (2) the first transfer learning across different circuits and technology nodes for BO, and (3) a selective transfer learning scheme to ensure only useful knowledge is utilized. These three novel components are integrated into BO with Multi-objective Acquisition Ensemble (MACE) to form Knowledge Alignment and Transfer Optimization (KATO) to deliver state-of-the-art performance: up to 2x simulation reduction and 1.2x design improvement over the baselines.