Enhancing ASIC Technology Mapping via Parallel Supergate Computing

TL;DR

This paper introduces a parallel supergate computing approach for ASIC technology mapping that significantly reduces computation time while improving delay optimization, leveraging parallel processing to balance efficiency and performance.

Contribution

It presents a novel parallel supergate generation method using input-constrained patterns, effectively balancing delay reduction and computational efficiency in ASIC design.

Findings

Achieved 4x speedup in computation time with 32 threads.

Realized 10.1 units delay reduction in experiments.

Demonstrated effective parallelization of supergate generation.

Abstract

With the development of large-scale integrated circuits, electronic design automation~(EDA) tools are increasingly emphasizing efficiency, with parallel algorithms becoming a trend. The optimization of delay reduction is a crucial factor for ASIC technology mapping, and supergate technology proves to be an effective method for achieving this in EDA tools flow. However, we have observed that increasing the number of generated supergates can reduce delay, but this comes at the cost of an exponential increase in computation time. In this paper, we propose a parallel supergate computing method that addresses the tradeoff between time-consuming and delay optimization. The proposed method utilizes the input-constrained supergate pattern to parallelly generate the supergate candidates, and then filter the valid supergates as the results. Experiment results show the efficiency of the proposed method, for example, it can attain the improvement of 4x speedup in computation time and 10.1 in delay reduction with 32 threads.