FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning

TL;DR

This paper proposes a novel FPGA placement method using deep reinforcement learning combined with a decomposition technique to efficiently minimize wirelength in large-scale placement problems.

Contribution

It introduces a learning-based FPGA placement approach with a new decomposition strategy to handle large search spaces, outperforming traditional search-based algorithms.

Findings

Reinforcement learning effectively minimizes wirelength in FPGA placement.

Decomposition improves scalability for large placement problems.

Empirical results demonstrate the method's effectiveness.

Abstract

This paper introduces the problem of learning to place logic blocks in Field-Programmable Gate Arrays (FPGAs) and a learning-based method. In contrast to previous search-based placement algorithms, we instead employ Reinforcement Learning (RL) with the goal of minimizing wirelength. In addition to our preliminary learning results, we also evaluated a novel decomposition to address the nature of large search space when placing many blocks on a chipboard. Empirical experiments evaluate the effectiveness of the learning and decomposition paradigms on FPGA placement tasks.