Combining Power and Arithmetic Optimization via Datapath Rewriting
Samuel Coward, Theo Drane, Emiliano Morini, George Constantinides

TL;DR
This paper introduces ROVER, an automated RTL optimization framework that combines arithmetic circuit rewriting and data/clock gating to reduce power consumption by up to 33.9% in datapath designs.
Contribution
It presents a novel approach that encodes multiple power optimization techniques as local rewrites, enabling simultaneous exploration and data-dependent power reduction.
Findings
Power consumption reduced by up to 33.9%.
Effective for open-source and industrial benchmarks.
Enables data-dependent, tailored circuit optimization.
Abstract
Industrial datapath designers consider dynamic power consumption to be a key metric. Arithmetic circuits contribute a major component of total chip power consumption and are therefore a common target for power optimization. While arithmetic circuit area and dynamic power consumption are often correlated, there is also a tradeoff to consider, as additional gates can be added to explicitly reduce arithmetic circuit activity and hence reduce power consumption. In this work, we consider two forms of power optimization and their interaction: circuit area reduction via arithmetic optimization, and the elimination of redundant computations using both data and clock gating. By encoding both these classes of optimization as local rewrites of expressions, our tool flow can simultaneously explore them, uncovering new opportunities for power saving through arithmetic rewrites using the e-graph data…
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Taxonomy
TopicsLow-power high-performance VLSI design · VLSI and FPGA Design Techniques · Embedded Systems Design Techniques
